Within serialization/deserialization (SERDES) applications, parallel data is transferred between a Physical Coding Sublayer (PCS) circuit block and a Physical Medium Attachment Sublayer (PMA) circuit block. PCS and PMA circuit blocks are part of the sublayers that help define the physical (PHY) layer of various communication protocols. PCS and PMA circuit blocks exist within communication protocols including, but not limited to, Fast Ethernet, Gigabit Ethernet, and 10 Gigabit Ethernet.
For example, the Ethernet PHY layer includes a Data Link Layer (Layer 2) and PHY Layer (Layer 1). The Data Link Layer includes a Logical Link Control Sublayer, a Media Access Control Sublayer, and a Reconciliation Sublayer. The PHY layer includes the PCS, the PMA, and a Physical Medium Dependent Layer. The PCS circuit block can perform functions such as auto-negotiation and coding, e.g., 8b/10b type coding. The PMA circuit block can perform functions such as framing, octet synchronization/detection, scrambling, and descrambling.
While the PCS and PMA circuit blocks operate at or about the same frequency, each of the two circuit blocks is controlled by a different clock. Conventional SERDES applications utilize a first-in-first-out (FIFO) memory to cross the clock domain boundary between the two circuit blocks. The FIFO memory accommodates for any clock skew that may exist between the PCS clock and the PMA clock. Within high speed circuit applications, however, the FIFO memory typically introduces an unacceptable amount of delay into the data path.